(1) Field of the Invention
The invention relates to a push-pull driver, and more particularly, to a high voltage, push-pull driver circuit compatible with standard CMOS devices.
(2) Description of the Prior Art
Input and output drivers are an especially challenging part of application specific integrated circuit (ASIC) design in advanced CMOS process. Advanced CMOS processes use very small device design rules, including shallow junctions and thin gate oxides. To compensate for these necessary device parameters, the internal voltage of the IC device is reduced to avoid voltage breakdown. However, it is usually necessary to maintain higher signal voltage levels external to the IC in order to maintain signal-to-noise ratios. In addition, external signals may be exposed to high voltage transient conditions; Therefore, the IC circuits that interface between the internal and external voltage levels are especially difficult to achieve.
Referring now to FIG. 1, a simplified output circuit for an integrated circuit is illustrated. In this circuit, a push-pull driver output is formed. In a push-pull driver, a switch P122 is provided to pull the output, OUT 10, to the upper rail voltage, VCC 26. A switch N114 is also provided to push OUT 10 to the lower rail, or ground, VSS 30. The output switches, P122 and N114 are controlled-such that only one switch is ON at any given time. The pull up driver may also be called a high side driver. The push down driver may also be called a low side driver.
In the example circuit, the VCC 26 level is biased to a relatively high-voltage compared to the internal VDD 50 voltage. For example, while the VDD 50 level is about 3 Volts, the VCC 26 is about 10 Volts. To handle the large voltage differential, the low voltage PFET devices, P122 and P218, are arranged in a cascade. The top PFET P122 has the gate terminal tied to the PFET switching signal, SWP 56, and is the switching device. The bottom PFET P218 is always biased ON. Typically, P122 and P218 are formed in separate n-wells and have source and bulk coupled. The voltage divider, R138 and R242, divides VCC 26 in half to create VCC/2 34.
The cascade arrangement and gate bias on P218 allows the low voltage PFET devices, P122 and P218, to effectively high side switch the VCC voltage 26 onto OUT 10. However, the arrangement suffers the disadvantage of a very limited VCC upper range. This is because this cascade structure cannot be effectively extended to greater than two cascaded devices without creating a sophisticated biasing circuit. It is essential that each PFET device in the cascade stack have a carefully regulated gate voltage so that gate oxide or gate-induced avalanche breakdown or drain-to-source punch through does not occur. Unfortunately, the cascade bias voltage cannot respond to changes in the output voltage.
In addition, the example push down, or low side driver, switch N114 suffers the disadvantage of insufficient gate drive. The NFET switching signal, SWN 58, is generated by the low voltage logic 46 that swings from VDD 50 to VSS 30. Therefore, the output NFET, N114, only has about a 3 Volt gate drive. To achieve a low impedance output, a very large NFET must be used. This costs a great amount of chip area.
Several prior art inventions describe output driver circuits. U.S. Pat. No. 6,081,132 to Isbara describes a push-pull CMOS driver with a cascaded PMOS section. The gate voltage of the cascaded devices is controlled using a biasing circuit. U.S. Pat. No. 6,157,223 to Blake teaches a push-pull CMOS driver with a cascaded PMOS section. The output voltage is fed back for gate biasing.
A principal object of the present invention is to provide an effective and very manufacturable high voltage, push-pull driver circuit.
A further object of the present invention is to provide a high voltage, push-pull driver that is compatible with standard CMOS.
A still further object of the present invention is to provide a high voltage, pull-up, or high side, driver using low voltage capable PFET devices.
A yet still further object of the present invention is to protect low voltage PFET devices by cascading devices.
Another yet still further object of the present invention is to protect the gate terminals of the PFET devices by limiting the gate voltage using a resistor network
Another yet still further object of the present invention is to enhance the ESD capability by providing gate resistance, gate-to-source capacitance, and gate-to-drain capacitance on each of the cascaded FET devices.
Another yet still further object of the present invention is to insure the ON state of the PFET devices by limiting the gate voltage using a diode network.
A still further object of the present invention is to provide a high voltage, push, or low side, driver
A yet still further object-of the present invention is to provide a boosted gate drive to reduce the ON resistance of a NFET output.
In accordance with, the objects of this invention, a new high voltage, high side driver circuit has been achieved. The circuit comprises, first, a top PFET having gate, drain, source, and bulk. The gate is coupled to a switching signal. The source is coupled to a high voltage. Second, a top resistor has first and second terminals. The first terminal is coupled to the high.voltage. Third, a middle PFET cell comprises, first, a middle PFET having gate, drain, source, and bulk. The source is coupled to the top PFET drain. The gate is coupled to the top resistor second terminal. A middle resistor has first and second terminals. The first terminal is coupled to the middle PFET gate. Finally, a middle means of clamping said middle PFET gate to a clamping voltage completes the middle PFET cell. Fourth, a bottom PFET cell comprises, first, a bottom PFET having gate, drain, source, and bulk. The gate is coupled to the middle resistor second terminal, the source is coupled to the middle PFET drain, and the drain forms a high side driver output. A bottom resistor is coupled between the bottom PFET gate and the high side driver output. Finally, a bottom means of clamping said bottom PFET gate to a clamping voltage completes the bottom PFET cell. The means of clamping may be a diode or a bipolar transistor.
Also in accordance with the objects of this invention, a new high voltage, low side driver circuit is achieved. The circuit comprises, first, an output NFET having gate, drain, and source. The source is coupled to ground, and the drain forms a low side driver output. A low voltage control means has an input and an output. The input and output voltages vary between ground and a low voltage. A diode is coupled between the low voltage control means output and the output NFET gate. Finally, a current mirror is coupled to the output NFET gate to pull the output NFET gate to a drive voltage above said low voltage to thereby reduce the ON resistance of the output NFET. The current mirror current is proportional to the output NFET drain current. The current mirror is switched OFF when the output NFET is OFF. The diode blocks the drive voltage from the low voltage control means.
Also in accordance with the objects of this invention, a new high voltage, low side driver circuit is achieved. The circuit comprises, first, a bottom NFET having gate, drain, source, and bulk. The gate is coupled to a switching signal, and the source is coupled to ground. Second, a bottom resistor has first and second terminals. The first terminal is coupled to ground. Third, a middle NFET cell comprises a middle NFET having gate, drain, source, and bulk. The source is coupled to the bottom NFET drain, and the gate is coupled to the bottom resistor second terminal. A middle resistor has first and second terminals. The first terminal is coupled to the middle NFET gate. A middle means of clamping the middle NFET gate to a clamping voltage completes the middle cell. Finally, a top NFET cell comprises, first, a top NFET having gate, drain, source, and bulk. The gate is coupled to the middle resistor second terminal, the source is coupled to the middle NFET drain, and the drain forms a low side driver output. A top resistor is coupled between the top NFET gate and the low side driver output. Finally, a top means of clamping the top NFET gate to the clamping voltage completes the top NFET cell.